The Big 3 EDA companies sell formal verification for $150K-$1M/year. Their tools say "PASS" -- you trust them. Ours produces a machine-checkable mathematical proof you can verify yourself.
The field is converging on formal methods + ML for hardware. Selected recent work.
LLM generates entire proofs for Isabelle/HOL. Proof repair loop on failures. 65.7% of theorems proved.
HardwareAWS uses Lean 4 to verify Arm instructions in Graviton processors. Production deployment of ITP for silicon.
LLM + RTLLLM generates SVA assertions from RTL. Automates the hardest part of formal verification setup.
GNN + CircuitsGNN learns circuit semantics from gate-level netlists. Predicts functional properties without simulation.
LLM + Lean 4Open-source framework for LLM interaction with Lean. Retrieval-augmented tactic prediction with ReProver.
ITP + HardwareCoq-based hardware verification at SiFive. Verified RISC-V processor components with proof certificates.
LLM + VerilogFine-tuned LLM generates synthesizable Verilog from natural language specs. 37x smaller than GPT-4, competitive quality.
Agents + FormalBest-first and beam search over Lean 4 tactic space. LLM proposes tactics, Lean kernel accepts or rejects.
LLM + VerilogMulti-turn LLM dialogue generates functional Verilog. 8-bit accumulator-based microprocessor designed entirely via conversation.
Formal + SafetyFormal methods for hardware security and safety. Covers information flow, side-channel, and fault injection verification.
LLM + FormalEvolving library of verified lemmas. LLM decomposes proofs into reusable blocks. Grows a skill library over time.
GNN + VerificationLarge-scale circuit graph dataset for ML-driven EDA. GNN benchmarks for timing, congestion, and IR drop prediction.
11 modules covering the checks that Synopsys, Cadence, and Siemens sell separately.
We're looking for design teams who want machine-checked verification on real silicon. Automotive, aerospace, datacenter -- if you need proof certificates, not just verdicts, reach out.